Search Thermo Fisher Scientific
Techniques for metrology, fault isolation, and defect identification in semiconductor packaging devices
The semiconductor packaging roadmap is swiftly evolving in both performance and complexity. Regardless of whether a device integrates chiplets, TSVs, micro-bumps, organic interposers, or ball grid arrays, numerous packaging challenges significantly impact process development. We have developed essential techniques for accurately measuring critical dimensions of these devices, along with essential techniques for fault isolation and defect identification.
Sample preparation of semiconductor packaging devices
FIB milling
Focused ion beam (FIB) milling is used to quickly remove material in specific locations, revealing 3D buried structures and defects. It finds extensive applications in packaged device analytical workflows. By employing cross-sectional FIB milling in conjunction with scanning electron microscope (SEM) imaging and analysis, you are able to swiftly identify the underlying causes of surface/near-surface defects and electrical faults. Exceptionally precise and high-quality FIB milling can be performed on a wide range of materials and length scales using the Thermo Scientific Helios 5 Hydra DualBeam. For defect analysis on complex wafer-level packages, the Thermo Scientific Helios 5 EXL Wafer DualBeam and Thermo Scientific Helios 5 PXL Wafer DualBeam systems are commonly used.
High-bandwidth memory micro-bump cross-section produced with FIB milling.
TEM sample preparation
TEM sample prep is a specialized technique within FIB milling that involves creating thin specimens for the purpose of TEM imaging and analysis. Though most packaging failure analysis workflows generally require SEM analysis, TEM analysis is now increasingly used to diagnose failures within the complex logic, memory and power die that are found in advanced packages. Rapidly creating precision TEM samples is a key capability of the Helios 5 EXL Wafer DualBeam, Thermo Scientific Helios 6 HD FIB-SEM, and the Helios 5 Hydra DualBeam systems.
Artifact-free TEM lamella preparation
Semiconductor delayering
Delayering is a sample preparation process that systematically removes material layer by layer, ensuring high-level planarity and uniformity. This technique is commonly employed in advanced packaging workflows. We offer highly automated solutions such as the Helios 5 PXL PFIB Wafer DualBeam for wafer-level delayering, which prepares the planar sample surface for wafer defect inspection. Additionally, the Helios 5 Hydra DualBeam is utilized for die-level delayering, enabling the preparation of sample surfaces for imaging or nanoprobing. Our proprietary gas chemistry ensures the planarity and uniformity of the delayering process, and we provide automated end-pointing capabilities that allow for precise stopping on any target layer within the BEOL interconnect structures.
Contact level semiconductor delayering.
Fault isolation of semiconductor packaging devices
Lock in thermography
Lock-in thermography is one of the most common and increasingly relied upon methods to localize defects in advanced packages. By powering up the device and utilizing high-sensitivity thermal optics, failure analysis engineers can analyze the thermal signature (or "hot spots") from the package and pinpoint specific areas of interest for further investigation. The Thermo Scientific ELITE System features high-sensitivity optics designed specifically to meet the requirements of semiconductor package FA.
Thermal hot spot captured by the ELITE System.
Imaging and analysis of semiconductor packaging devices
TEM imaging and analysis
TEM data is increasingly needed for precise analysis of defects within die-to-die and die-to-wafer interconnects and also within individual die themselves. The Thermo Scientific Talos F200E TEM enables rapid TEM imaging and defect analysis, supported by X-ray energy dispersive spectroscopy (EDS). Buried physical defects, residue from etching processes, and micro-cracking may all require high-resolution TEM analysis. For researchers investigating the next generation of materials to be incorporated into semiconductor packaging schemes, the Thermo Scientific Spectra Ultra (S)TEM provides exceptional analytical data.
TEM image and EDS map of a FinFET in semiconductor analysis
SEM imaging and analysis
Packaging and assembly facilities increasingly rely on SEM applications to investigate surface, near-surface, and buried defects. Gaining access to these defects requires high-speed removal of packaging materials to expose a high-quality, artifact-free area for imaging and analysis. The complex array of materials found in most packages, along with the relatively large (micron-scale) volume removal involved, requires some form of plasma FIB-based milling prior to in situ SEM imaging rather than relying on Ga FIB or laser milling. The Helios 5 PX Wafer DualBeam and Helios 5 Hydra DualBeam are both ideally suited to performing such high-resolution SEM imaging and analysis.
UHR SEM analysis of TSV fill quality and TSV liner coverage
3D image reconstruction
3D reconstruction involves utilizing SEM or TEM images obtained from a volume of material to create a 3D dataset. Thermo Scientific DualBeam instruments offer a practical solution for this process. By employing precision milling, DualBeams enable the memory device structures to be incrementally removed in thin slices, all while capturing high-resolution SEM images. These images can then be reconstructed using Thermo Scientific Avizo Software, allowing for a comprehensive visualization of the memory device structure. This approach provides valuable insights into the fabrication process and enables a deeper understanding of the device's characteristics.
3D reconstruction of TSV structures for semiconductor analysis
Electrostatic discharge
ESD compliance
Electrostatic discharge can damage small features and structures in semiconductors and integrated circuits. The Thermo Scientific MK Test Systems and the Thermo Scientific Orion3 Electrostatic Discharge Testers were designed to verify that your devices meet targeted electrostatic discharge compliance standards.
This graph highlights the eight-V/I configuration that can be utilized on the MK.4TE ESD system to understand how your device will perform in different high-voltage conditions.
For Research Use Only. Not for use in diagnostic procedures.